This check creates USER_CLOCK_VTREE_TYPE =
interSLR constraints that update the clock tree routing on a specific clock
net to improve performance on SLR crossings. It offers an advantage over the
place_design -clock_vtree_type switch as it targets a
specific net as opposed to all nets in a design. It leverages a previous design run to
capture information on the performance of a clock and the placement of the clock loads
to determine whether to offer the alternative template.
The suggestion triggers when all of the following conditions are met:
- The device is an AMD Versal™ multi-SLR device.
- Report QoR Suggestions is run post place or post route.
- Failing timing paths cross an SLR.
- Clock performance exceeds the limit of the balanced clock tree for SLR crossings.
- The clock does not qualify for calibrated deskew.
This check works after routing, but it is most effective when you run it after
placement, before the Vivado router adds clock skew. In most cases,
RQS_CLOCK-26 offers better performance than a change in clock
template.
The following are related suggestions:
-
RQS_CLOCK-1 -
RQS_CLOCK-26