RQS_AMD_NETLIST-12: GT Floorplan Synthesis Constraints - 2025.2 English - UG906

When you create a hierarchical floorplan, preserve hierarchy at synthesis to prevent logic optimizations that can cause timing issues later in the flow. For example, if you optimize GT control logic that was coded to be replicated on each side of the device and in different SLRs, the optimization can result in that logic being shared between all GTs. This sharing can create timing problems later in the flow. Using KEEP_HIERARCHY during synthesis prevents this optimization.

This suggestion selects the same hierarchies chosen for floorplanning when you use RQS_AMD_NETLIST-11. It is strongly recommended to apply RQS_AMD_NETLIST-12 before using RQS_AMD_NELTIST-11.