This check creates Pblock constraints for GT-related logic. It checks for
advanced primitive usage, identifies related GT connections, and creates a Pblock
sized appropriately for those connections. This helps guide the placer. It is
recommended to use this suggestion with RQS_AMD_NETLIST-12.
The check can create three sizes of Pblocks:
- A single clock region
- A three clock region horizontal row
- A three clock region side of an SLR
The Pblocks are based on the hierarchical cell connected to the GT output clocks.
| Property | Value |
|---|---|
| APPLICABLE_FOR |
place_design
|
| AUTO |
1
|