QoR Assessment Details - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The QoR Assessment Details table summarizes design issues in five categories that form the basis of the report_qor_assessment score:

  • Utilization
  • Netlist
  • Clocking
  • Congestion
  • Timing
Figure 1. QoR Assessment Details

Each category receives an OK status when no sub-items are marked REVIEW. If any sub-item requires attention, the failing item appears with its threshold and current value. These thresholds are not hard limits, but exceeding them can make timing closure more difficult. Focus on items that exceed thresholds significantly or appear in multiple categories.

Items marked with an asterisk (*) do not directly affect the QoR score but can still impact timing closure and require review.

Utilization

Vivado checks utilization across the entire device, including SLR and Pblock levels. Run report_qor_suggestions to reduce utilization if needed.

Netlist

Netlist checks evaluate the logical structure and non-timing constraints. Vivado flags issues such as:

  • Use of the DONT_TOUCH property
  • High fanout nets with poor driver profiles
  • Other netlist features that can challenge implementation

Clocking

Vivado checks for high clock skew on setup and hold paths.

  • If a skew issue is detected, Vivado automatically includes path details in the report.
  • In text mode, use the ‑csv_output_dir <directory> option to generate timing paths in CSV format.
  • Run report_qor_suggestions to receive automated fixes for skew problems.

Congestion

Vivado evaluates netlist structures that can lead to routing congestion. Congested region data becomes available after placement.

You can:

  1. Run place_design and route_design to assess congestion.
  2. Use report_qor_suggestions to generate cell-specific congestion fixes.

Timing

Vivado reviews the 100 worst-case paths per clock group. It checks:

  • Worst negative slack (WNS)
  • Total negative slack (TNS)
  • Worst hold slack (WHS)
  • Total hold slack (THS)

To help identify potential failures earlier in the flow, Vivado also performs:

  • Net budget checks: Adds conservative delay values for nets instead of estimated values.
  • LUT budget checks: Replaces estimated LUT delays with more conservative values.

Review and resolve paths with negative slack early to reduce late-stage timing issues. Use the Challenging Timing Paths section in the Vivado IDE or export the data to a CSV file for further review.

If the design is routed and is either the UltraScale or UltraScale+ architectures, Vivado also checks whether the last mile flow used by Intelligent Design Runs can close timing. This analysis includes:

  • Worst-case paths
  • Slack before and after optimization
  • Involved logic primitives

These details help determine whether the design can meet final timing goals.