Pulse width checks are rule checks on signal waveforms as they reach hardware primitives after propagating through the device. These checks usually reflect functional limits set by the internal circuitry of the primitive. For example, the minimum period check on a DSP clock pin ensures that the clock driving a DSP instance doesn’t exceed the maximum frequency tolerated by the DSP.
Pulse width checks do not affect synthesis or implementation. Their analysis must be performed at least one time before generating the bitstream like any other design rule check in the Vivado Design Suite.
A pulse width violation usually comes from an incorrect clock definition,
failing pulse width or period checks. It can also result from excessive skew in the
clock topology, failing max_skew. Review the AMD FPGA data sheet for your target device to understand
the valid operating range for the primitive where the violation happens.
If the violation is due to skew, simplify the clock tree or place clock resources closer to the affected pins to reduce the skew.