Pulse Width Area (Pin Switching Limits) - 2025.2 English - UG906

The Pulse Width area of the Design Timing Summary shows results for all checks related to pin switching limits. These checks include the following:

• Minimum low pulse width
• Minimum high pulse width
• Minimum period
• Maximum period
• Maximum skew (between clock pins of the same leaf cell, such as PCIe® or GT on AMD UltraScale™ devices)

The report provides the following values:

Worst Pulse Width Slack (WPWS)

The worst slack across all pulse width-related checks, using both min and max delays.

Total Pulse Width Slack (TPWS)

The sum of all WPWS violations, based on the worst violation per pin.

• Value is 0 ns when all pulse width constraints are met
• Value is negative when violations exist

Number of Failing Endpoints

The number of pins with WPWS violations (slack less than 0 ns).

Total Number of Endpoints

The total number of pins analyzed for pulse width checks.