Phase Shift in Timing Reports - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

A positive phase shift moves the source clock edge forward, delaying the clock edge. A negative phase shift moves the source clock edge backward. When you modify the clock waveform, you can cause the static timing analysis to use different clock edges for the source and capture clocks.

In the following examples, the MMCM auto-derives the clock clkout0 with a period of 10 ns.

No Phase Shift

vivado% set_property CLKOUT0_PHASE 0.000 [get_cells qpll/plle2_adv_inst]
vivado% report_timing
...
(clock clkout0 rise edge) 0.000 0.000 r
...
        MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                               -5.411  5.903 r mmcm_inst/mmcm_adv_inst/CLKOUT0
...

The source clock edge is at 0.0 ns.

Positive Phase Shift of 12.0 with PHASESHIFT_MODE=WAVEFORM 

vivado% set_property CLKOUT0_PHASE 12.000 [get_cells qpll/plle2_adv_inst]
vivado% report_timing
...
(clock clkout0 rise edge) 0.333 0.333 r
...
    MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                          -5.411  5.903 r mmcm_inst/mmcm_adv_inst/CLKOUT0
...

The source clock edge is delayed by 0.333 ns (10 ns / 360 × 12.0).

Positive Phase Shift of 12.0 with PHASESHIFT_MODE=LATENCY 

vivado% set_property CLKOUT0_PHASE 12.000 [get_cells qpll/plle2_adv_inst]
vivado% report_timing
...
(clock clkout0 rise edge) 0.000 0.000 r
...
    MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                          -5.078   6.236 r mmcm_inst/mmcm_adv_inst/CLKOUT0 
...

The MMCM insertion delay is increased by 0.333 ns (10 ns / 360 × 12.0). The source clock edge remains at 0.0 ns.

Negative Phase Shift of –15.0 with PHASESHIFT_MODE=WAVEFORM 

vivado% set_property CLKOUT0_PHASE -15.000 [get_cells qpll/plle2_adv_inst]
vivado% report_timing
...
(clock clkout0 rise edge) -0.417 -0.417 r
...
     MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                           -5.411  5.903 r mmcm_inst/mmcm_adv_inst/CLKOUT0
...

The source clock edge moved backward by –0.417 ns (10 ns / 360 × –15.0).

Negative Phase Shift of –15.0 with PHASESHIFT_MODE=LATENCY 

vivado% set_property CLKOUT0_PHASE -15.000 [get_cells qpll/plle2_adv_inst]
vivado% report_timing
...
(clock clkout0 rise edge) 0.000 0.000 r
...
     MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                           -5.828   5.486 r mmcm_inst/mmcm_adv_inst/CLKOUT0 
...

The MMCM insertion delay decreased by 0.417 ns (10 ns / 360 × –15.0). The source clock edge remains at 0.0 ns.