You can find clock phase shift information in the Clock Report, which you generate
using the
report_clocks command. When an MMCM/PLL clock
is phase-shifted with PHASESHIFT_MODE set to LATENCY, the tool marks the auto-derived clock with
attribute S.In the Generated Clocks section of the clock report, you see the pin phase shift the tool accounts for in the MMCM/PLL insertion delay.
Note: The report only includes the delay from
the auto-derived clock phase shift. It doesn’t include the phase shift the tool includes
in the MMCM/PLL insertion delay.
In the following example below, the MMCM has PHASESHIFT_MODE set to LATENCY. The
auto-derived clock clk_out1_clk_wiz_0 has no phase
shift defined for the MMCM pin CLKOUT0, while clk_out2_clk_wiz_0 includes a –90 degree phase shift
defined for CLKOUT2.
Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode
Clock Period(ns) Waveform(ns) Attributes Sources
clk_in1 10.000 {0.000 5.000} P {clk_in1}
clk_out1_clk_wiz_0 10.000 {0.000 5.000} P,G,A {clknetwork/inst/mmcme3_adv_inst/CLKOUT0}
clk_out2_clk_wiz_0 10.000 {0.000 5.000} P,G,A,S {clknetwork/inst/mmcme3_adv_inst/CLKOUT2}
====================================================
Generated Clocks
====================================================
Generated Clock : clk_out1_clk_wiz_0
Master Source : clknetwork/inst/mmcme3_adv_inst/CLKIN1
Master Clock : clk_in1
Multiply By : 1
Generated Sources : {clknetwork/inst/mmcme3_adv_inst/CLKOUT0}
Generated Clock : clk_out2_clk_wiz_0
Master Source : clknetwork/inst/mmcme3_adv_inst/CLKIN1
Master Clock : clk_in1
Multiply By : 1
Pin Phase Shift(ns) : -2.5 (-90 degrees)
Generated Sources : {clknetwork/inst/mmcme3_adv_inst/CLKOUT2}