Path from Input Port to Output Port - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

In this path, data traverses the device without being latched inside the device. This is commonly called an in-to-out path.

  • The input clock and output clock can be either a virtual clock or a design clock.
  • Input and output delays are defined relative to that clock.