Path from Input Port to Internal Sequential Cell - 2025.2 English - UG906

In this path, data follows these steps:

1. A clock on the board launches the data outside the device.
2. The data reaches the device input port after a delay, known as the input delay (as defined by Synopsys design constraints (SDC)).
3. The data then propagates through the internal logic of the device and reaches a sequential cell that is clocked by the destination clock.