The following test case can be used to review the synthesis log file and determine whether the RTL can be improved to guide the tool toward a more optimal implementation.
This example describes a 40K-deep, 36-bit-wide memory in VHDL, requiring a 16-bit address bus.
Using the report_utilization command post-synthesis shows that the
synthesis tool generates 72 block RAMs.
Manual calculation reveals that fewer block RAMs are actually needed:
- Break the memory into two parts: 32K × 36 and 8K × 36.
- Use an address decoder based on the MSB address bits to enable one memory or the other for read/write operations and select the proper output data.
- The 32K × 36 memory can be implemented with 32 RAMBs: 4 × 8 × (4K × 9).
- The 8K × 36 memory can be implemented with 8 RAMBs: 8 × (1K × 36).
- The total optimal number of RAMBs required is 40.
The synthesis log file includes details on how each memory is configured and mapped to FPGA primitives. In this case, the memory depth is treated as 64K, indicating that non–power-of-two depths are not handled optimally.
The synthesis tool uses 64K × 1 (two block RAMs with cascade feature), repeated 36 times for the 36-bit data width. This results in 36 × 2 = 72 block RAMs.
Applying the revised RTL forces synthesis to infer the optimal number of RAMBs.