The following figure illustrates a multi-clock fanin example. In this structure, both
clk_a and clk_x transfer data through
combinatorial logic (LUT2) to a synchronizer circuit in the
clk_b domain.
Figure 1. Multi-Clock Fanin Example
To improve the mean time between failures (MTBF), first synchronize the source data from
clk_a and clk_x individually. Then combine the
synchronized data using interconnect or FPGA logic. This approach also prevents glitches
from propagating into the destination clock domain.