Multi-Bit Synchronizer - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The multi-bit synchronizer groups multiple single-bit synchronizers based on startpoint and endpoint cell names, as well as matching CDC rules.

To be identified as a multi-bit bus:

  • The startpoint and endpoint cell names must use the format baseName[index].
  • The corresponding index values must match between the startpoints and endpoints.

If some bits of the bus match different CDC rules, the report splits the bus into segments or single bits that share the same rule.

Figure 1. Multi-Bit Synchronizer with 2-Bit Width

Important Considerations

  • A register-based synchronizer alone does not guarantee the safety of a multi-bit domain crossing.
  • The CDC engine reports rule CDC-6 (multi-bit synchronizer) as a warning because it cannot confirm the safety of the bus structure and needs to be reviewed by the user.
  • You must review and determine whether the synchronization topology is appropriate for your design.

Safe Usage

If the bus is gray coded, you can safely use a register-based synchronizer on all bits, provided you apply appropriate timing constraints. This ensures only one data transition occurs at a time in the destination clock domain.

Unsafe Usage

If the bus is not gray coded, consider using alternative synchronization techniques such as clock enable (CE) controlled CDC or multiplexer (MUX) controlled CDC.