The clocks <clock_name> and
<clock_name> are timed together but have
no phase relationship. The design could fail in hardware. The clocks originate from
two parallel clock modifying blocks and at least one of the MMCM, PLL, or XPLL input
clock dividers is not set to 1. To be safely timed, all MMCMs, PLLs, or XPLLs
involved in parallel clocking must have the clock divider set to 1.