The clocks <clock_name> and
<clock_name> are timed together but have
no phase relationship. The design could fail in hardware. One of the clocks
originates from the DPLL <cell> that is not
using the phase detector, or its incoming clock is not connected to the CLKIN_DESKEW pin. Under these conditions, it is unsafe
to time between the master clock of the DPLL and its auto-derived clock (or
downstream generated clocks) because the relationship between the clocks is
unknown.