Max/Min Delays for Output Buses - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

Vivado detects output buses and reports the following:

  • Worst-case maximum and minimum delay
  • Bus skew, calculated by using one bit as a reference and measuring offset of all other bits. The worst offset is the skew for the entire bus.