For source-synchronous output interfaces, use the Groups tab to define a custom group with a forwarded clock as the reference port. Vivado reports the following:
- Skew and delay relative to the reference port
- A structure similar to the output bus section, but based on your defined reference port
For example, you are grouping ports for DDR output skew calculation. To
calculate output skew for a DDR interface, you can group multiple signals relative to a
forwarded clock port. For example, if the group includes the following and the reference
(forwarded) clock is rldiii_ck_n[0], use the Tcl
command below.
-
rldiii_a[0–19] -
rldiii_ba[0–3] -
rldiii_ref_n -
rldiii_we_n
report_datasheet -group [get_ports {rldiii_ck_n[0] rldiii_a[*] rldiii_ba[*]
rldiii_ref_n rldiii_we_n}] -name timing_1The first port in the group list is treated as the reference pin for skew and delay calculations.
Vivado uses multi-corner analysis to calculate worst-case data across all
defined process corners. If you include the -show_all_corners option,
the report shows the worst-case data separately for each corner.
The resulting datasheet report reflects timing behavior under a range of operating conditions. The following figure shows an example output for the DDR interface group.