Manual cell placement achieves the best performance on a device. Designers often use it on a small portion of the design, such as logic around a high-speed I/O interface, or for block RAMs and DSPs. Manual placement can be slow.
All floorplanning techniques can require significant engineering time and multiple iterations. If cell names change, update the floorplan constraints.
When floorplanning:
- Know the final pinout
- Fix I/Os to provide anchor points for the floorplan
- Place blocks that communicate with I/Os near their I/Os
Figure 1. I/O Components Pulling Design Apart
Tip: If the pinout is pulling a
block apart, consider:
- Modifying the pinout
- Modifying the RTL
- Constraining only block RAMs and DSPs
- Unplacing I/O registers if external timing requirements allow