MMCM/PLL Phase Shift Modes - 2025.2 English

MMCM/PLL Phase Shift Modes - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID

UG906

Release Date

2025-12-10

Version

2025.2 English

During timing analysis, you can model clock phase shift in two ways by setting the PHASESHIFT_MODE property on the MMCM or PLL. The two options are:

Table 1. MMCM/PLL PHASESHIFT_MODE Properties
PHASESHIFT_MODE Property	Phase-Shift Modeling	Comment
WAVEFORM	Models the phase shift by modifying the clock waveform.	Apply `set_multicycle_path –setup` constraints to adjust the timing requirements for clock domain crossing paths from or to the phase-shifted clock.
LATENCY	Models the phase shift as insertion delay through the MMCM or PLL.	Does not require additional multicycle path constraints.

The default phase-shift mode varies by AMD FPGA family, but you can override the default on each MMCM or PLL as needed.

Table 2. Default MMCM/PLL Clock Phase Shift Handling
Technology	Default MMCM/PLL Clock Phase Shift Handling
7 series	Clock waveform modification (WAVEFORM)
AMD UltraScale™	Clock waveform modification (WAVEFORM)
AMD UltraScale+™	MMCM/PLL insertion delay (LATENCY)
AMD Versal™ adaptive SoC	MMCM/PLL insertion delay (LATENCY)

Important: The PHASESHIFT_MODE property affects only the static timing analysis engine’s slack computation. It does not change the actual device configuration. Switching between WAVEFORM and LATENCY modes can require updates to your timing constraints, which can affect design timing.

Important: If a phase shift is defined on any of the CLKOUTx pins and multiple clocks reach the input pins of the MMCM/PLL, using PHASESHIFT_MODE=LATENCY is invalid. This triggers the warning: Timing 38-437. In this case, set PHASESHIFT_MODE=WAVEFORM.

Using PHASESHIFT_MODE=LATENCY is especially helpful when you want to introduce skew between two clocks to meet timing. You do not need to add multicycle path constraints when the phase shift is negative, zero, or positive.

Migrating a legacy design from 7 series or UltraScale to UltraScale+ without setting PHASESHIFT_MODE defaults phase shift modeling to latency. In that case, you should review and typically remove any multicycle path constraints that were originally used to account for phase shift. You can identify these constraints by running report_methodology. Look for TIMING-31, which flags multicycle paths between clocks when one is phase-shifted and generated by an MMCM/PLL with PHASESHIFT_MODE=LATENCY.

Both the clocking wizard and the high speed SelectIO™ wizard allow you to force the clock phase-shift modeling on each MMCM/PLL. The PHASESHIFT_MODE property is automatically saved in the IP XDC file.