Locking Specific Logic to Device Sites - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

You can place cells on specific locations on the FPGA, such as assigning all I/O ports in an AMD 7 series FPGA design. Place the I/Os before attempting to close timing.

I/O placement can influence cell placement in the FPGA fabric. Manually placing other cells in the fabric can help create consistent clock logic and macro placement, improving the consistency of implementation runs.

Table 1. Constraints Used to Place Logic
Constraint Use Notes
LOC Places a gate or macro at a specific site. SLICE sites contain subsites called BEL sites.
BEL Specifies the subsite in the slice to use for a basic element.