When transferring between sequential cells or ports, the data is:
- Launched by one of the edges of the source clock, which is called the launch edge.
- Captured by one of the edges of the destination clock, which is called the capture edge.
In a typical timing path, data transfers between two sequential cells within one clock period:
- The launch edge occurs at 0 ns.
- The capture edge occurs one clock period later.
The following section explains how these edges define the setup and hold relationships used in timing analysis.