The following figure shows a LUTRAM read/write potential collision. In this example, data is written to the LUTRAM using the write clock, and the output is captured using the read clock.
When the read and write addresses differ, no CDC path exists between the write and read clocks. However, when the addresses match, a CDC path forms between the write clock and the read clock.
To prevent this CDC condition, ensure that the logic surrounding the LUTRAM never generates the same read and write addresses during active read and write operations. When this condition is guaranteed, you can waive the associated CDC violation.
AMD's FIFO generator intellectual property (IP), for example, includes built-in logic to prevent read/write collisions by design.