Interconnect - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

Use this setting to control how Vivado calculates net delays in the timing report. You can base delays on estimated placement, actual routing, or exclude them entirely. By default, Vivado sets this option to Estimated for post-synthesis designs and Actual for post-implementation designs.

The equivalent Tcl command is set_delay_model.

Estimated

  1. For unplaced cells, Vivado estimates delay based on ideal placement, driver characteristics, load type, and fanout. Nets are labeled unplaced in the report.
  2. For placed cells, delay is based on the actual distance between the driver and load and is labeled estimated in the report.

Actual

For routed designs, delay reflects the real hardware delay of the routed net. These nets are labeled routed in the report.

None

Vivado excludes interconnect delays and sets all net delays to zero.