Inter-Clock Paths Section - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The Inter-Clock Paths section of the Timing Summary Report shows the worst slack and total violations for timing paths between different source and destination clocks.

Figure 1. Timing Summary Report Inter-Clock Paths Details

To view detailed information:

  1. In the left index pane, click any entry under Inter-Clock Paths.
  2. Review the slack and violation summary for each clock pair.
  3. Examine the N-worst paths reported for each analysis type:
    • Setup
    • Hold
    • Pulse Width
    The N-worst paths are determined by the -max_paths value in the Tcl command option or by the maximum number of paths per clock or path group set in the GUI.

Use this section to analyze cross-clock domain timing interactions and identify any violations that might require constraint adjustments or design changes.