An intelligent design run (IDR) is a specialized implementation run that uses a complex flow to attempt timing closure. Because an IDR can be aggressive, expect a compile time about 3.5 times longer than a standard run.
The IDR provides a simple interface for complex timing closure features and can achieve results comparable to those of FPGA experts for a high percentage of designs.
Note: Intelligent Design Runs are not available for AMD Versal™
architectures. As an alternative, use the
instructions found in the Automatically Generating and Applying Suggestions section to
automatically generate and apply suggestions.