Information Reuse - 2025.2 English - UG906

Reuse placement and timing information from a design that met timing if your current design does not consistently meet timing.

1. Open two implementation runs:
   • One that meets timing
   • One that does not meet timing
     Tip: On a system with multiple monitors, click Open Implementation in New Window to view designs side by side.
2. Identify failing timing paths in the run that does not meet timing using report_timing_summary.
3. On the run that meets timing, run report_timing in min_max mode for those same paths.
4. Compare the timing results:
   1. Clock skew
   2. Datapath delay
   3. Placement
   4. Route delays
5. If logic delay differs between path endpoints, review the synthesis runs.