Improving Critical Logic on RAMB Outputs - 2025.2 English

Improving Critical Logic on RAMB Outputs - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID

UG906

Release Date

2025-12-10

Version

2025.2 English

This test case demonstrates how to improve critical paths through logic restructuring, such as pushing a macro (block RAM) closer to the destination register.

Figure 1. 16x1 Multiplexer Connected to Block RAM Outputs

In this example, a 16×1 multiplexer has only one input from a block RAM; the remaining inputs are fed by registers. The critical path is block RAM → 2 logic levels → flip-flop (FF).

Figure 2. Critical RAMB-LUT-FF Path

The figure shows the critical path in red, from block RAM to FF. The path has two logic levels from block RAM to FF, as well as FF to FF. Because the block RAM CLK→Q delay is higher than for registers, the block RAM to FF path is critical.

Figure 3. RTL Code Snippet

The logic can be restructured for better results. In this example, the original code is rewritten by breaking the 16×1 multiplexer into two multiplexers. The condition for select value 4'd5 is exempted and used as an enabling condition for a 2×1 multiplexer.

Figure 4. Cascade Multiplexer Structure to Reduce RAMB Output Logic Levels

This cascade multiplexer structure results in FF→FF with three logic levels, but reduces the block RAM to FF path to a single logic level. This improves the block RAM to FF path and helps downstream tools achieve better placement, because RAMB placement is more challenging than LUT or FF placement. In general, reducing the number of long paths around macro primitives such as RAMB, UltraRAM, and DSP yields better QoR.