This chapter explains timing closure techniques that you can use in addition to those described in the UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292) and UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).
- Use intelligent design runs to automate the timing closure flow. This approach solves complex timing closure issues and requires minimal user knowledge.
- Apply the QoR suggestion object flow to automatically enhance QoR by setting properties.
- Use the ML strategy flow to help you select optimal tool options for your design.
- Apply floorplanning to guide the placer. This advanced technique can improve timing paths and reduce congestion.
- Check if your design has issues meeting hold time requirements, as this can be a key factor in choosing your timing closure strategy.