Hold/Removal (Min Delay Analysis) - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

Use the following combinations for min delay analysis:

  • source clock (Slow_min), datapath (Slow_min), destination clock (Slow_max)
  • source clock (Fast_min), datapath (Fast_min), destination clock (Fast_max)
Important:
  • Delays from different corners are never mixed on the same path when calculating slack.
  • Most setup or recovery violations occur with slow corner delays.
  • Most hold or removal violations occur with fast corner delays. However, because this is not always true, especially for I/O timing, AMD recommends performing both max and min delay analyses on both corners.