Hierarchical floorplanning places one or more hierarchy levels into a region on the chip. This region guides the placer at a global level, and the placer handles detailed placement.
Advantages Over Gate-Level Floorplanning
- Creation is faster than gate-level floorplanning
- Can improve timing
- Less sensitive to design changes
- The hierarchy level acts as a container for all gates and generally works even if the netlist changes
Using Hierarchical Floorplanning
- Identify the lower-level hierarchies containing the critical path.
- Use the top-level floorplan to choose where to place them.
- Let implementation place individual cells.
- Leverage the tool’s knowledge of cell connectivity and timing paths for fine-grain placement.