Global Clock Source Details Table - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The Global Clock Source Details table shows how each clock generator output connects to global clocks and provides timing clock information. The following figure illustrates how the outputs of an MMCM instance (src0 and src1) connect to clock buffers. In the example, the CLKOUT2 output of src1 drives two global clocks: g7 and g8.

Figure 1. Global Clock Source Details Table

The table includes the following columns:

Table 1. Global Clock Source Details Columns
Column Description
Source Id Identifier of the clock-generating primitive
Global Id Identifiers of the global clocks driven by the source pin
Driver Type/Pin Output primitive pin that generates the clock
Constraint Highest-priority user-defined constraint applied to the clock buffer, using the following order:
  1. LOC
  2. PBLOCK
Site Clock source location set by you or by the Vivado implementation tools
Clock Region Clock region of the device where the source is located
Clock Loads Number of clock pin loads connected to the source pin
Non-Clock Loads Number of non-clock pin loads connected to the source pin, such as CE pins on FDCE elements
Source Clock Period Period in nanoseconds of the timing clock generated by the source pin. If multiple clocks propagate, the report shows the smallest period
Clock Name of the timing clock generated by the source pin. If multiple clocks propagate, the report displays Multiple
Driver Pin Logical name of the clock source pin
Net Logical name of the clock net segment connected to the source pin