The Global Clock Resources table provides a summary for each clock net, including key constraint and placement details, as shown in the following figure.
Figure 1. Global Clock Resources Table
The table includes the following columns:
| Column | Description |
|---|---|
| Global Id | Unique identifier for each global clock net |
| Source Id | Identifier for the clock-generating primitive connected to the clock buffer |
| Driver Type/Pin | Primitive pin that drives the clock net |
| Constraint | Highest-priority user-defined physical constraint applied to the clock
buffer, following this order:
|
| Site | Location of the clock buffer, set by you or by the Vivado implementation tools |
| Clock Region |
Device clock region where the buffer is located. Does not apply to 7 series. |
| Root | Device clock region where the clock net CLOCK_ROOT is placed
(not applicable to 7 series) |
| Clock Delay Group | User-defined group of clock nets to enforce matching of the clock routing (not applicable to 7 series) |
| Load Clock Region | Number of clock regions containing loads driven by the clock net |
| Clock Loads | Number of cells connected through clock pins |
| Non-Clock Loads | Number of cells connected through non-clock pins, such as CE pins on FDCE elements |
| Clock Period | Period in nanoseconds of the timing clock on the net; if multiple clocks propagate, the smallest period is shown |
| Clock | Name of the timing clock on the net; if multiple clocks propagate, the report
displays Multiple
|
| Driver Pin | Logical name of the clock driver pin |
| Net | Logical name of the clock net segment connected to the driver pin |
GCLK_DESKEW
|
Indicates if deskew calibration is enabled (Versal only) |
CLOCK_EXPANSION_WINDOW
|
Reports the CLOCK_EXPANSION_WINDOW
property after placement (Versal
only) |
| Clock Low Fanout | Indicates if the CLOCK_LOW_FANOUT property is applied |