Floorplanning is the process of guiding placement and routing to improve performance, consistency, and timing closure in your design. While the Vivado tools automatically place and route most designs successfully, some designs require additional direction to meet timing goals or achieve predictable results between implementation runs.
You can apply floorplanning at different levels of details, from broad hierarchical guidance to precise cell-level placement. In each case, the goal is to influence how the placer organizes logic on the device so that related elements are physically close together, route delays are reduced, and specialized resources are used efficiently.
Common reasons to use floorplanning include:
- A design has never met timing, or does not meet timing consistently
- Timing is sensitive to placement of high-speed I/O interfaces, clock logic, or macros
- Critical paths span multiple regions of the device, especially in SSI devices with multiple SLRs
- Specialized resources such as block RAM, DSPs, and transceivers must be organized to reduce congestion and route length
The topics covered in this section include: