SSI devices consist of multiple super logic regions (SLRs) joined by an interposer. The interposer connections, called super long lines (SLLs), introduce additional delay when crossing from one SLR to another.
Follow these guidelines:
- Keep SLR boundaries in mind when structuring the design, generating a pinout, and floorplanning.
- Minimize SLL crossings by keeping critical timing path logic inside a single SLR.
- Place I/Os in the same SLR as the associated I/O interface circuitry.
- Carefully plan clock placement when laying out logic for SSI devices.
- Let the placer perform an automatic placement before attempting extensive manual partitioning. Review the results for floorplanning opportunities you might not have considered.