The following figure illustrates a simplified fanout scenario. In this example, a single flip-flop in the
clk_a domain drives a net that is
synchronized three separate times in the clk_b domain, highlighted in
red.Figure 1. Simplified Fanout Example
This structure is discouraged because the multiple synchronizers introduce latency that is bounded but not cycle-accurate. The misaligned timing can cause data coherency issues in the destination clock domain.
Note: A fanout of N signals to N different clock
domains is not considered a CDC problem and does not trigger a
CDC-11
violation. See the Asynchronous Reset Synchronizer section for safe
examples of reset signal fanout.