In this example, two MMCM outputs generate the clocks. The BUFGCE_DIV output produces a
divisional clock,
clk1, whose master clock comes from
CLKOUT0. CLKOUT1 produces a generated clock,
clk2. If you add the following constraint, Vivado
issues a TIMING-47
warning:set_clock_groups -asynchronous
-group [get_clocks clk1]
-group [get_clocks clk2]Figure 1. False Path, Asynchronous Clock Group, or Max Delay Datapath Only Constraint
between Synchronous Clocks
Because both clk1 and clk2 originate from the same MMCM,
they are synchronous. Data crossing between these domains is under synchronous CDC and
does not require set_clock_groups -asynchronous.