In the following figure, a synchronous clock domain crossing exists between
clk1 and clk2. Both clocks are considered
synchronous by default, but no common node relationship is detected. If synthesized
out-of-context and the clocks have a common node at the top level, you can suppress the
violation with constraints such as:
create_clock -period 3.000 [get_ports clk1]
set_property HD.CLK_SRC BUFGCTRL_X0Y2 [get_ports clk1]
create_generated_clock -divide_by 2 -source [get_ports clk1] [get_ports clk2]
set_property HD.CLK_SRC BUFGCTRL_X0Y4 [get_ports clk2]
Figure 1. No Common Node Between Related Clocks