The following constraint is written by the user and is applied on the datapath in between
the two registers as shown in the following schematic, where the CE pin
of the destination register is connected to VCC:
set_multicycle_path -setup -end -from [get_clocks -of [get_ports -scoped_to_current_instance s_axi_ctrl_aclk]] -to [get_clocks -of [get_ports -scoped_to_current_instance s_axi_hwa_aclk]] 2Figure 1. Multicycle Path with Tied CE Pins Example
Check whether data is changed at every clock edge outside the scope of the multicycle
path. If it does, make sure to add the required logic tied to the CE
pin.
The following figure shows a flop-to-flop path that has the proper clock enable logic tied to
the CE pin, making the flop enable on alternating clock cycles:
set_multicycle_path 2 -setup -from [get_pins data0_reg/C] -to [get_pins data1_reg/D]Figure 2. Flop-to-Flop Path
Figure 3. Timing Diagram
