The following example uses a counter design.
The signal cnt counts from 0 to 16, which requires a 5-bit vector
to encode.
In this example, the post-route critical path schematics shows the
endpoint as bit 30 of the cnt signal. After selecting
the startpoint and endpoint cells of the critical path, you can visualize the equivalent
path in the elaborated view by opening a schematic of the selected cells and expanding
the logic from the endpoint pin back to the startpoint.
The elaborated view shows that the adder input has been sized to 32 bits because the
signal cnt is declared as an integer. In this case, the 32-bit operator
is retained throughout synthesis optimizations. The elaborated view reveals this
behavior, which indicates a possible RTL improvement.
Because the counter increments from 0 to 16, you can define a range for the
cnt signal. This change forces the adder inputs to be 5 bits wide
instead of 32 bits wide.
This RTL change impacts synthesis optimization, which you can verify in the elaborated view without going through the entire compilation flow.