The following constraint is applied to the datapath between the two registers shown in the schematic, where the CE pin of the destination register is tied to VCC:
set_multicycle_path -setup -end -from [get_clocks -of [get_ports -scoped_to_current_instance s_axi_ctrl_aclk]] -to [get_clocks -of [get_ports -scoped_to_current_instance s_axi_hwa_aclk]] 2Figure 1. Multicycle Path with Tied CE Pins Example
Verify whether the data changes at every clock edge outside the scope of the multicycle path. If it does, add the necessary logic connected to the CE pin.
The following example shows a flop-to-flop path with proper clock enable logic tied to the CE pin. This configuration enables the flop on alternating clock cycles:
set_multicycle_path 2 -setup
-from [get_pins data0_reg/C]
-to [get_pins data1_reg/D]Figure 2. Flop-to-Flop Path
Figure 3. Timing Diagram
