In the following figure, a synchronous clock domain crossing (CDC) exists between
the clk1 and clk2 domains. Both clk1
and clk2 are determined to be synchronous in Vivado
by default. However, because clk1 and clk2 are input ports, there is no common node relationship between the two
clocks. For this case, Vivado Design Suite cannot guarantee that the
two clocks are synchronous.
However, if the module is synthesized Out-Of-Context and clk1 and
clk2 have a common node at the top-level, the TIMING-7 violation
can be suppressed during the OOC synthesis by defining, for example, the following
constraints:
create_clock -period 3.000 [get_ports clk1]
set_property HD.CLK_SRC BUFGCTRL_X0Y2 [get_ports clk1]
create_generated_clock -divide_by 2 -source [get_ports clk1] \
[get_ports clk2]
set_property HD.CLK_SRC BUFGCTRL_X0Y4 [get_ports clk2]Figure 1. No Common Node Between Related Clocks