Example - Example - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2026-06-23
Version
2026.1 English

In the following figure, a create_generated_clock constraint is created on the output of the LUT1 inverter, but the -invert switch is not applied.

Figure 1. Invalid Waveform Redefinition on a Clock Tree
Page-1 Sheet.1 Sheet.2 Process Process.5 Invalid waveform redefinition on clock tree Invalid waveform redefinition on clock tree Sheet.5 Sheet.7 X15527-111715 X15527-111715