Example: Reporting the Timing Exceptions Affecting the Timing Analysis - 2025.2 English - UG906

This example shows how to apply timing exceptions and use the report_exceptions command to identify how those constraints affect the design. The design is fully constrained, with clock and I/O delays defined relative to clk.

Figure 1. Fully Constrained Design for Timing Exception Example

1. Select Window > Timing Constraints.
2. In the Timing Constraints window, add the following timing exceptions to the design:

   set_multicycle_path 3 -from [get_cell int10_reg] -to [get_cell int20_reg]
   set_multicycle_path 4 -to [get_cell int20_reg]
   set_false_path -from [get_ports in6] -to [get_cell int20_reg]
   set_false_path -to [get_ports out5] 
   set_false_path -to [get_cells int21_reg]
   set_false_path -from [get_ports in6] -to [get_ports out6]
   set_max_delay 5 -to [get_ports out6]
   set_min_delay 3 -from [get_cells int10_reg] -to [get_cell int20_reg]

   The Timing Constraints window now displays each applied constraint and assigns a position number to each.

   
   
   
3. Run the report_exceptions Tcl command in the console.
   
   
4. Review the Report Exceptions Output. The report shows the following:

   Position

   The constraint's position number, which matches the order in the Timing Constraints window

   From, Through, and To

   The pattern or object used with the *-from, *-through, or *-to options (an asterisk means the option wasn't used)

   Setup and Hold

   Which checks the constraint applies to, including the following:

   • cycles= for set_multicycle_path
   • false for set_false_path
   • max= for set_max_delay
   • max_dpo= for set_max_delay -datapath_only
   • min= for set_min_delay
   • clock_group= for set_clock_group

   Status

   Describes whether the constraint is partially or fully overridden, and which type of exception caused it.

   • MCP = multicycle path
   • FP = false path
   • MXD = max delay
   • MND = min delay
   • CG = clock group