Example NoC QoS Analysis - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The following example shows an IP integrator design with two AXI Traffic Generators and two AXI Block RAM Controllers, each connected to embedded memory. This example demonstrates adjusting data width and PL clock frequency to achieve the same bandwidth.

  • axi_traffic_gen_64, axi_bram_ctrl_64, and emb_mem_gen_64 use 64-bit data widths and connect to a 200 MHz clock (green).
  • axi_traffic_gen_128, axi_bram_ctrl_128, and emb_mem_gen_128 use 128-bit data widths and connect to a 100 MHz clock (purple).

Both traffic generators connect to their respective Block RAM controllers through the NoC. The required read/write bandwidth for each connection is 1000 MB/sec.

Figure 1. Example IP Integrator Block Design

After validating the design in IP integrator, the initial NoC solution routes each connection through the horizontal NoC.

Figure 2. Initial NoC Solution

The QoS report for this solution shows that the bandwidth requirements are met and that each connection has a structural latency of 26 NoC clock cycles.

Figure 3. Initial NoC QoS Report