The tool runs DRCs on the elaborated design to check for issues related to the following:
- I/O
- Clock placement
- Potential coding problems in your HDL
- XDC constraints
Because the RTL netlist excludes many I/O buffers, clock buffers, and other primitives found in post-synthesis designs, the tool checks fewer conditions at this stage. Elaborated design DRCs are less comprehensive than those run later in the flow.