Determining if Hold-Fixing is Negatively Impacting the Design - 2025.2 English - UG906

The Vivado router prioritizes fixing hold timing before setup timing. A design might still function in the lab if setup is failing by a small amount because you can lower the clock frequency. However, if hold timing fails, the design most likely does not function.

In most cases, the router can meet hold timing without affecting setup timing. In some cases, often caused by design or constraint errors, setup timing can be significantly degraded.

Improper hold checks are commonly caused by incorrect set_multicycle_path constraints that omit the -hold option. Large hold requirements can also result from excessive clock skew. In this case, review the clocking architecture for the affected circuit. See Identifying Timing Violations Root Cause in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).

This issue can occur when the design meets setup timing after placement but fails setup timing after routing. To investigate, use the report_design_analysis command with the -show_all option to view path delay caused by routing detours that the router adds to fix hold violations.

Figure 1. Report Design Analysis with Hold Fix Detour

If you suspect hold fixing is affecting timing closure, use one of these methods:

• Method 1: Routing without Hold Fixing
• Method 2: Checking Hold Timing on the Worst Failing Setup Path