Description - Description - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2026-06-23
Version
2026.1 English

The DRC warning occurs when a set_max_delay -datapath_only constraint is overridden by a set_clock_groups or set_false_path constraint between clocks. If a point-to-point set_false_path constraint overrides a set_max_delay -datapath_only constraint, the DRC is not reported.