Input/output (I/O) timing is based on paths that involve external devices. The input and output delays specify the path delay of the ports relative to a clock edge at the interface. Missing these constraints can result in an FPGA interface that fails to meet the external device timing requirements.
Note: A TIMING-18 violation is reported for any missing
clock edge. If a clock is inverted during clock network propagation and a required delay
is missing for the falling edge, a violation is still generated.