The CLK and CLKDIV pins of an OSERDESE3 have a strict skew requirement that must not be exceeded. Placing the clock sources for CLK and CLKDIV in a different SLR than the OSERDESE3 can increase clock path delay and cause max skew violations.
The CLK and CLKDIV pins of an OSERDESE3 have a strict skew requirement that must not be exceeded. Placing the clock sources for CLK and CLKDIV in a different SLR than the OSERDESE3 can increase clock path delay and cause max skew violations.