Description - 2025.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-05-29
Version
2025.1 English

When the output pin of a clocking primitive has multiple generated or auto-derived clocks present, these clocks cannot be available on hardware simultaneously. To match static timing analysis with hardware behavior, provide physically or logically exclusive clock group constraints between these clocks. Otherwise, some clock pairs are timed although they do not exist in hardware.